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tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 1 post office box 1443 ? houston, texas 772511443 organizatio n...524288 by 8 bits single 5-v power supply industry standard 32-pin dual in-line package and 32-lead plastic leaded chip carrier all inputs / outputs fully ttl compatible static operation (no clocks, no refresh) max access / min cycle time v cc 10% '27c/ pc040-10 100 ns '27c/ pc040-12 120 ns '27c/ pc040-15 150 ns 8-bit output for use in microprocessor-based systems power-saving cmos technology 3-state output buffers 400-mv assured dc noise immunity with standard ttl loads latchup immunity of 250 ma on all input and output pins no pullup resistors required low power dissipation (v cc = 5.5 v) activ e... 275 mw worst case standb y... 0.55 mw worst cas e (cmos-input levels) temperature range options description the tms27c040 devices are 524 288 by 8-bit (4 194 304-bit), ultraviolet (uv) light erasable, electrically programmable read-only memories (eproms). the TMS27PC040 devices are 524 288 by 8-bit (4 194 304-bit), one-time programmable (otp) electrically programmable read-only memories (proms). these devices are fabricated using cmos technology for high speed and simple interface with mos and bipolar circuits. all inputs ( including program data inputs) can be driven by the series 74 ttl circuits. each output can drive one series 74 ttl circuit without external resistors. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 3213231 14 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 430 15 16 17 18 19 20 tms27c040 j package ( top view ) pin nomenclature a0 a18 address inputs dq0 dq7 inputs (programming) / outputs e chip enable g output enable gnd ground v cc 5-v supply v pp 13-v power supply 2 2 only in program mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v pp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd v cc a18 a17 a14 a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 a14 a13 a8 a9 a11 g a10 e dq7 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 dq3 dq4 dq5 a12 a15 a16 v a18 a17 TMS27PC040 fm package ( top view ) dq6 pp gnd v cc copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 2 post office box 1443 ? houston, texas 772511443 description (continued) the data outputs are 3-state for connecting multiple devices to a common bus the tms27c040 is offered in a 600-mil ceramic dual-in-line package (j suffix). the tms27c040 is offered with two choices of temperature ranges of 0 c to 70 c (jl suffix) and 40 c to 85 c (je suffix). (see table 1.) the TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package ( fm suffix). the TMS27PC040 is offered with two choices of temperature ranges of 0 c to 70 c ( jl suffix) and 40 c to 85 c (je suffix). table 1. temperature range suffixes function suffix for operating free-air temperature ranges 0 c to 70 c 40 c to 85 c tms27c040-xxx jl je TMS27PC040-xxx fml fme these eproms and proms operate from a single 5-v supply ( in the read mode), and they are ideal for use in microprocessor-based systems. one other (13 v) supply is needed for programming. all programming signals are ttl level. for programming outside the system, existing eprom programmers can be used. operation the seven modes of operation are listed in t able 2. the read mode requires a single 5-v supply. all inputs are ttl level except for v pp during programming (13 v), and v h (12 v) on a9 for the signature mode. table 2. operation modes mode function 2 mode e g v pp v cc a9 a0 dq0 dq7 read v il v il x v cc x x data out output disable v il v ih v cc v cc x x hi-z standby v ih x v cc v cc x x hi-z programming v il v ih v pp v cc x x data in program inhibit v ih v ih v pp v cc x x hi-z verify v ih v il v pp v cc x x data out signature mode v il v il v cc v cc v 3 v il mfg code 97 signat u re mode v il v il v cc v cc v h 3 v ih device code 50 2 x can be v il or v ih 3 v h = 12 v 0.5 v read/ output disable when the outputs of two or more tms27c040s or TMS27PC040s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. to read the output of a single device, a low level signal is applied to the e and g pins. all other devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins. latchup immunity latchup immunity on the tms27c040 and TMS27PC040 is a minimum of 250 ma on all inputs and outputs. this feature provides latchup immunity beyond any potential transients at the p.c. board level when the eprom is interfaced to industry standard ttl or mos logic devices. the input / output layout approach controls latchup without compromising performance or packing density.
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 3 post office box 1443 ? houston, texas 772511443 power down active i cc supply current can be reduced from 50 ma to 1 ma by applying a high ttl input on e and to 100 m a by applying a high cmos input on e . in this mode all outputs are in the high-impedance state. erasure ( tms27c040) before programming, the tms27c040 eprom is erased by exposing the chip through the transparent lid to a high intensity uv-light (wavelength 2537 ?). the recommended minimum exposure dose (uv intensity exposure time) is 15-w ? s/cm 2 . a typical 12-mw / cm 2 , filterless uv lamp erases the device in 21 minutes. the lamp must be located about 2.5 cm above the chip during erasure. after erasure, all bits are in the high state. normal ambient light contains the correct wavelength for erasure; therefore, when using the tms27c040, the window must be covered with an opaque label. after erasure (all bits in logic high state), logic lows are programmed into the desired locations. a programmed low can be erased only by uv light. initializing ( TMS27PC040) the otp TMS27PC040 prom is provided with all bits in logic high state, then logic lows are programmed into the desired locations. logic lows programmed into an otp prom cannot be erased. snap! pulse programming the tms27c040 and TMS27PC040 are programmed by using the snap! pulse programming algorithm. the programming sequence is shown in the snap! pulse programming flow chart shown in figure 1. the initial setup is v pp = 13 v, v cc = 6.5 v, e = v ih , and g = v ih . once the initial location is selected, the data is presented in parallel (eight bits) on pins dq0 through dq7. once addresses and data are stable, the programming mode is achieved when e is pulsed low (v il ) with a pulse duration of t w(pgm) . every location is programmed only once before going to interactive mode. in the interactive mode, the word is verified at v pp = 13 v, v cc = 6.5 v, e = v ih , and g = v il . if the correct data is not read, the programming is performed by pulling e low with a pulse duration of t w(pgm) . this sequence of verification and programming is performed up to a maximum of 10 times. when the device is fully programmed, all bytes are verified with v cc = v pp = 5 v 10%. program inhibit programming can be inhibited by maintaining high level inputs on the e and g pins. program verify programmed bits can be verified with v pp = 13 v when g = v il , and e = v ih . signature mode the signature mode provides access to a binary code identifying the manufacturer and type. this mode is activated when a9 (pin 26) is forced to 12 v. two identifier bytes are accessed by toggling a0. all other addresses must be held low. the signature code for the tms27c040 is 9750. a0 low selects the manufacturer's code 97 (hex), and a0 high selects the device code 50 (hex), as shown in table 3. table 3. signature mode identifier 2 pins identifier 2 a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex manufacturer code v il 1 0 0 1 0 1 1 1 97 device code v ih 0 1 0 1 0 0 0 0 50 2 e = g = v il , a1-a8 = v il , a9 = v h , a10-a18 = v il , v pp = v cc .
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 4 post office box 1443 ? houston, texas 772511443 start address = first location v cc = 6.5 v 0.25 v, v pp = 13 v 0.25 v last address? address = first location x = 0 v cc = v pp = 5 v 0.5 v compare all bytes to original data device passed increment address increment address verify one byte program one pulse = t w = 100 m s x = 10? x = x + 1 last address? device failed pass no yes yes no fail fail pass no program mode interactive mode final verification yes program one pulse = t w = 100 m s figure 1. snap! pulse programming flow chart
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 5 post office box 1443 ? houston, texas 772511443 logic symbol 2 18 [pwr dwn] & en a a a a a a a a a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 e g 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 eprom 524 288 8 13 14 15 17 18 19 20 21 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a 0 524 287 0 a17 a18 31 30 2 this symbol is in accordance with ansi / ieee std 91-1984 and iec publication 617-12. pin numbers are for the j package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage range, v cc (see note 1) 0.6 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v pp (see note 1) 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range (see note 1), all inputs except a9 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . a9 0.6 v to 13 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, with respect to v ss (see note 1) 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range ('27c040-_ _jl and '27pc040-_ _fml) 0 c to 70 c . . . . . . . . . . . . . . operating free-air temperature range ('27c040-_ _je and '27pc040 _ _ fme) 40 c to 85 c . . . . . . . . . . . storage temperature range, t stg 65 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to gnd.
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 6 post office box 1443 ? houston, texas 772511443 recommended operating conditions min nom max unit v cc su pp ly voltage read mode (see note 2) 4.5 5 5.5 v v cc s u ppl y v oltage snap! pulse programming algorithm 6.25 6.5 6.75 v v pp su pp ly voltage read mode v cc 0.6 v cc + 0.6 v v pp s u ppl y v oltage snap! pulse programming algorithm 12.75 13 13.25 v v ih high level dc in p ut voltage ttl 2 v cc + 0.5 v v ih high - le v el dc inp u t v oltage cmos v cc 0.2 v cc + 0.5 v v il low level dc in p ut voltage ttl 0.5 0.8 v v il lo w- le v el dc inp u t v oltage cmos 0.5 0.2 v t a operating free-air temperature '27c040-_ _jl '27pc040-_ _fml 0 70 c t a operating free-air temperature '27c040-_ _je 40 85 c note 2: v cc must be applied before or at the same time as v pp and removed after or at the same time as v pp . the device must not be inserted into or removed from the board when v pp or v cc is applied. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature parameter test conditions min max unit v oh high level dc out p ut voltage i oh = 400 m a 2.4 v v oh high - le v el dc o u tp u t v oltage i oh = 20 m a v cc 0.1 v v ol low level dc out p ut voltage i ol = 2.1 ma 0.4 v v ol lo w- le v el dc o u tp u t v oltage i ol = 20 m a 0.1 v i i input current (leakage) v i = 0 v to 5.5 v 1 m a i o output current (leakage) v o = 0 v to v cc 1 m a i pp1 v pp supply current v pp = v cc = 5.5 v 10 m a i pp2 v pp supply current (during program pulse) v pp = 12.75 v 50 ma i cc1 v cc su pp ly current (standby) ttl-input level v cc = 5.5 v, e = v ih 1 ma i cc1 v cc s u ppl y c u rrent (standb y ) cmos-input level v cc = 5.5 v, e = v cc 100 m a i cc2 v cc supply current (active) e = v il ,v cc = 5.5 v t cycle = minimum cycle time, outputs open 2 50 ma 2 minimum cycle time = maximum access time. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 mhz 3 parameter test conditions min typ max unit c i input capacitance v i = 0 v 4 8 pf c o output capacitance v o = 0 v 8 12 pf 3 all typical values are at t a = 25 c and nominal voltages. capacitance measurements are made on sample basis only.
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 7 post office box 1443 ? houston, texas 772511443 switching characteristics over recommended ranges of operating conditions (see notes 3 and 4) parameter test conditions '27c040-10 '27 pc040-10 '27c040-12 '27 pc040-12 '27c040-15 '27 pc040-15 unit min max min max min max t a(a) access time from address 100 120 150 ns t a(e) access time from chip enable c l = 100 p f, 100 120 150 ns t en(g) output enable time from g c l = 100 f , 1 series 74 50 50 50 ns t dis output disable time from g or e , whichever occurs first ttl load, input t r 20 ns, in p ut t f 20 ns 0 50 0 50 0 50 ns t v(a) output data valid time after change of address, e , or g , whichever occurs first 2 input t f ? ?? ?? 2 ???? ????????? ??? ?? ????? ?? ?????? ???? ????? ???? ? ??? ??? ????????? ??????????????? ??? ???? ???? ?????? ??? ? ? ?? ?? ? ????? ????????? ??? ??? ?? ? ? ??? ?? ??? ???? ??? ? ? ??? ????? ??? ???? ????? ?? ????? ???? ?????????? ??? ??? ? ??? ???? ????? ????????? switching characteristics for programming: v cc = 6.5 v and v pp = 13 v (snap! pulse), t a = 25 c (see note 3) parameter min max unit t dis(g) output disable time from g 0 100 ns t en(g) output enable time from g 150 ns note 3: for all switching characteristics the input pulse levels are 0.4 v to 2.4 v. timing measurements are made at 2 v for log ic high and 0.8 v for logic low. (see figure 2) timing requirements for programming min nom max unit t w(pgm) pulse duration, program snap! pulse programming algorithm 95 100 105 m s t su(a) setup time, address 2 m s t su(e) setup time, e 2 m s t su(g) setup time, g 2 m s t su(d) setup time, data 2 m s t su(vpp) setup time, v pp 2 m s t su(vcc) setup time, v cc 2 m s t h(a) hold time, address 0 m s t h(d) hold time, data 2 m s
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 8 post office box 1443 ? houston, texas 772511443 parameter measurement information 2.08 v r l = 800 w c l = 100 pf (see note a) output under test 2 v 0.8 v 2 v 0.8 v 2.4 v 0.4 v notes: a. c l includes probe and fixture capacitance. b. ac testing inputs are driven at 2.4 v for logic high and 0.4 v for logic low. timing measurements are made at 2 v for logic h igh and 0.8 v for logic low for both inputs and outputs. figure 2. ac testing output load circuit and waveform a0 a18 e addresses valid t a(a) t a(e) g dq0 dq7 hi-z t en(g) t v(a) t dis output valid v ih v il v ih v il v ih v il v ih v il hi-z figure 3. read-cycle timing
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 9 post office box 1443 ? houston, texas 772511443 parameter measurement information t en(g) a0 a18 dq0 dq7 v pp v cc address stable v ih v il v ih / v oh v il / v ol v pp 2 v cc v cc 2 v cc program verify t su(a) t h(a) t su(d) t su(vpp) t su(vcc) t su(e) t h(d) t su(g) t w(pgm) t dis(g) data-in stable data-out stable e g v ih v il v ih v il hi-z 2 13-v v pp and 6.5-v v cc for snap! pulse programming figure 4. program-cycle timing (snap! pulse programming)
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 10 post office box 1443 ? houston, texas 772511443 fm (r-pqcc-j32) plastic j-leaded chip carrier 4040201-4 / b 03/95 0.020 (0,51) 0.015 (0,38) seating plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) nom 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) typ 0.030 (0,76) 0.547 (13,89) 30 1 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 5 4 20 13 14 29 21 0.050 (1,27) 0.004 (0,10) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-016
tms27c040 524288 by 8-bit uv erasable TMS27PC040 524288 by 8-bit programmable read-only memory smls040f november 1990 revised september 1997 11 post office box 1443 ? houston, texas 772511443 j (r-cdip-t**) ceramic side-braze dual-in-line package 4040084 / b 04/95 b c 0.018 (0,46) min 0.125 (3,18) min 0.022 (0,56) 0.012 (0,30) 0.014 (0,36) 0.008 (0,20) seating plane a wide 24 a pins** dim max min narr 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.235(31,37) 1.235(31,37) 1.265(32,13) 1.265(32,13) min max b c max min 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) narr 32 wide 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) narr 28 wide wide 40 narr 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.032(51,61) 2.032(51,61) 2.068(52,53) 2.068(52,53) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 24 pin shown 1 12 24 13 0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) lens protrusion 0.010 (0,25) max 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0 10 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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